The present invention relates to electronic circuits, and more particularly, to techniques for phase interpolation.
A digital periodic clock signal is often used to sample a data signal that is transmitted to an integrated circuit from an external source. Different techniques can be used to align the rising and falling edges of the clock signal with respect to a sampling window of the data signal so that the data signal can be sampled accurately. As the clock signal frequency and the data rate increases, the sampling window decreases, and the sampling timing is more constrained. A phase interpolator circuit is an example of a circuit that can be used to generate a desired phase shift in a high frequency sampling clock signal.
FIG. 1A illustrates a prior art phase interpolator system. The system of FIG. 1A includes a control block 10, a multiplexer block 15, slew rate circuits 21-24, and phase interpolator 30. The system of FIG. 1A was fabricated in the Stratix® IV GX field programmable gate array manufactured by Altera Corporation of San Jose, Calif. Phase interpolator 30 includes two differential pairs formed by n-channel MOSFETs 41-44 and variable current sources 51-52.
A phase interpolator circuit can generate any one of a number of different phases in a periodic output signal in response to periodic input signals. A phase interpolator circuit can generate a sinusoidal output voltage signal VOUT that is a weighted sum of two sinusoidal voltage input signals, as shown in equations (1)-(3).VOUT=(α×sin(ωt))+(β×cos(ωt))=c×sin(ωt+θ)  (1)c=√{square root over (α2+β2)}  (2)θ=arctan(β/α)  (3)
The phase interpolator can generate a phase shift θ in VOUT between 0° and 360° relative to an input clock signal. A desired phase shift in VOUT can be generated by setting the values of the control codes α and β as a weighted summation of two variable current sources, such as current sources 51-52.
In the system of FIG. 1A, multiplexers in multiplexer block 15 select four of the clock signals C0, C45, C90, C135, C180, C225, C270, and C315 as output clock signals CLKA, CLKB, CLKC, and CLKD based on control signals from control block 10. The four selected clock signals CLKA, CLKB, CLKC, and CLKD are transmitted to slew rate circuits 21-24. Slew rate circuits 21-24 convert clock signals CLKA, CLKB, CLKC, and CLKD into four signals that are more sinusoidal in shape. The four sinusoidal signals are transmitted to the gate terminals of transistors 41-44 in phase interpolator 30 as cos ωt, −cos ωt, sin ωt, and −sin ωt, respectively. Phase interpolator 30 generates periodic output signals OUT0 and OUT180.
The four selected clock signals CLKA, CLKB, CLKC, and CLKD determine which one of 8 different 45° wide regions RG0-RG7 between 0° and 360° the phase shift in OUT0 occurs in. FIG. 1B illustrates the 8 regions RG0-RG7 between 0° and 360°. Clock signals C0, C45, C90, C135, C180, C225, C270, and C315 have relative phases of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°, respectively. Multiplexer block 15 selects the 4 clock signals shown in one of the columns of Table 1 below as clock signals CLKA, CLKB, CLKC, and CLKD to generate a phase shift in OUT0 that is within the region indicated in the top row of that column.
TABLE 1RegionRG0RG1RG2RG3RG4RG5RG6RG7cosωtC0C45C90C135C180C225C270C315−cosωtC180C225C270C315C0C45C90C135sinωtC45C90C135C180C225C270C315C0−sinωtC225C270C315C0C45C90C135C180
Control block 10 includes an 8-bit shift register that controls the weight current ratios of current sources 51-52 and a 3-bit counter that selects the region RG0-RG7 that the phase of OUT0 is generated in. The currents through current sources 51-52 are varied to change the phase shift of OUT0 within the selected region RG0-RG7.